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integrated circuit systems, inc. ICS952906A 1236a?08/06/07 recommended application: via vn800/cn700/p4m800 style chipset for p4 processor output features: 3 - 0.7v current-mode differential cpu pairs 10 - pci, 3 free running, 33mhz 2 - ref, 14.318mhz 3 - 3v66, 66.66mhz 1 - 48mhz 1 - 24/48mhz 2 - 25mhz @ 2.5v key specifications: cpu/src outputs cycle-cycle jitter < 125ps 3v66 outputs cycle-cycle jitter < 250ps pci outputs cycle-cycle jitter < 250ps cpu - agp skew < +/- 350ps agp-pci skew between 1~3.5ns programmable timing control hub? for next gen p 4 ? processor features/benefits: programmable output frequency. programmable asynchronous 3v66&pci frequency. programmable output divider ratios. programmable output skew. programmable spread percentage for emi control. watchdog timer technology to reset system if system malfunctions. programmable watch dog safe frequency. support i2c index read/write and block read/write operations. uses external 14.318mhz reference input. 48-pin ssop & tssop *fs1/ref0 1 48 vdda **fs0/ref1 2 47 gnd vddref 3 46 iref x1 4 45 cpuclkt_itp/(pci_stop#) x2 5 44 cpuclkc_itp/(cpu_stop#) gnd 6 43 gnd **fs2/pciclk_f0 7 42 cpuclkt1 **fs4/pciclk_f1 8 41 cpuclkc1 pciclk_f2 9 40 vddcpu vddpci 10 39 cpuclkt0 gnd 11 38 cpuclkc0 **mode/pciclk0 12 37 gnd pciclk1 13 36 25mhz_0 pciclk2 14 35 25mhz_1 pciclk3 15 34 vdd2.5 pciclk4 16 33 vttpwr_gd/pd# vddpci 17 32 sdata gnd 18 31 sclk pciclk5 19 30 reset# pciclk6 20 29 3v66_0 **fs3/48mhz 21 28 gnd **sel24_48#/24_48mhz 22 27 vdd3v66 gnd 23 26 3v66_1 vdd48 24 25 3v66_2 * this pin have 120k pull-up to vdd ** this pin have 120k pull-down to gnd ics952906 bit4 bit3 bit2 bit1 bit0 cpu agp pci fs4fs3fs2fs1fs0 mhz mhz mhz 00000 100.00 66.67 33.33 00001 200.00 66.67 33.33 00010 133.33 66.67 33.33 00011 166.67 66.67 33.33 00100200.0066.6733.33 00101 400.00 66.67 33.33 00110 266.67 66.67 33.33 00111 333.33 66.67 33.33 01000 100.99 67.33 33.66 01001 201.98 67.33 33.66 01010 134.65 67.33 33.66 01011 168.31 67.32 33.66 01 1 00 115.00 76.67 38.33 01101 230.00 76.67 38.33 01110 153.33 76.66 38.33 01111 191.67 76.67 38.33 1 0000 100.00 66.66 33.33 10001 200.00 66.66 33.33 10010 133.33 66.66 33.33 10011 166.67 71.43 35.71 1 0100200.0066.6633.33 10101 400.00 66.66 33.33 10110 266.67 66.66 33.33 10111 333.33 66.66 33.33 11000 105.00 69.99 35.00 11001 210.00 69.99 35.00 11010 140.00 69.99 35.00 11011 175.00 69.99 35.00 11 1 00 110.00 73.33 36.66 11101 220.00 73.33 36.66 11110 146.66 73.33 36.66 11111 183.34 73.33 36.66 functiona lity pin configuration
2 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 pin description pin # pin name pin type description 1 *fs1/ref0 i/o frequency select latch input pin / 14.318 mhz reference clock. 2 **fs0/ref1 i/o frequency select latch input pin / 14.318 mhz reference clock. 3 vddref pwr ref, xtal power supply, nominal 3.3v 4 x1 in crystal input, nominally 14.318mhz. 5 x2 out crystal output, nominally 14.318mhz 6 gnd pwr ground pin. 7 **fs2/pciclk_f0 i/o frequency select latch input pin / 3.3v pci free running clock output. 8 **fs4/pciclk_f1 i/o frequency select latch input pin / 3.3v pci free running clock output. 9 pciclk_f2 out free running pci clock not affected by pci_stop# . 10 vddpci pwr power supply for pci clocks, nominal 3.3v 11 gnd pwr ground pin. 12 **mode/pciclk0 i/o function select latch input pin, 0=desktop mode (pin 44/45 are outputs), 1=mobile mode (pin44/45 are stop inputs) / pci clock output. 13 pciclk1 out pci clock output. 14 pciclk2 out pci clock output. 15 pciclk3 out pci clock output. 16 pciclk4 out pci clock output. 17 vddpci pwr power supply for pci clocks, nominal 3.3v 18 gnd pwr ground pin. 19 pciclk5 out pci clock output. 20 pciclk6 out pci clock output. 21 **fs3/48mhz i/o frequency select latch input pin / fixed 48mhz clock output. 3.3v 22 **sel24_48#/24_48mhz i/o latched select input for 24/48mhz output / 24/48mhz clock output. 1=24mhz, 0 = 48mhz. 23 gnd pwr ground pin. 24 vdd48 pwr power pin for the 48mhz output.3.3v 25 3v66_2 out 3.3v 66.66mhz clock output 26 3v66_1 out 3.3v 66.66mhz clock output 27 vdd3v66 pwr power pin for the 3.3v 66mhz clocks. 28 gnd pwr ground pin. 29 3v66_0 out 3.3v 66.66mhz clock output 30 reset# out real time system reset signal for frequency gear ratio change or watchdog timer timeout. this signal is active low. 31 sclk in clock pin of smbus circuitry, 5v tolerant. 32 sdata i/o data pin for smbus circuitry, 3.3v tolerant. 33 vttpwr_gd/pd# in this 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. this is an active high input. / asynchronous active low input pin used to power down the device into a low power state. 34 vdd2.5 pwr power supply, nominal 2.5v 35 25mhz_1 out 25mhz clock output, 2.5v 36 25mhz_0 out 25mhz clock output, 2.5v 37 gnd pwr ground pin. 38 cpuclkc0 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 39 cpuclkt0 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 40 vddcpu pwr supply for cpu clocks, 3.3v nominal 41 cpuclkc1 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 42 cpuclkt1 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 43 gnd pwr ground pin. 44 cpuclkc_itp/(cpu_stop#) i/o complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. / stops all cpuclk besides the free running clocks 45 cpuclkt_itp/(pci_stop#) i/o true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. / stops all pciclk besides the free running clocks 46 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 47 gnd pwr ground pin. 48 vdda pwr 3.3v power for the pll core.
3 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 ICS952906A is a 48 pin clock chip for via vn800/cn700/p4m800 style chipsets. when used with a fanout ddr buffer, such as the 93788, it provides all the necessary clock signals for such a system. the ICS952906A is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). this part incorporates ics's newest clock technology which offers more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. m/n control can configure output frequency with resolution up to 0.1mhz increment. general description block diagram i ref reset# pll2 frequency dividers programmable spread pll1 programmable frequency dividers stop logic 48mhz 24_48mhz x1 x2 xtal sdata sclk pci_stop# cpu_stop# vttpwrgd#/pd# fs (4:0) sel24_48# mode control logic ref (1:0) cpuclkt (1:0)/itp cpuclkc (1:0)/itp 25mhz (1:0) 3v66 (2:0) pciclk (6:0) pciclk_f (2:0) power groups vdd gnd 3 6 ref, xtal 10, 17 11, 18 pciclk outputs 24 23 48mhz fix, fix digital, fix analog 27 28 3v66 outputs 34 37 2.5v for 25mhz outputs 40 43 cpu outputs 48 47 cpu analog, cpu digital description pin number
4 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 general i 2 c serial interface information for the ICS952906A how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
5 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 table1: quadrom frequency selection table bit4 bit3 bit2 bit1 bit0 cpu agp pci spread fs4fs3fs2fs1fs0 mhz mhz mhz % 0 0 0 0 0 0 0 100.00 66.67 33.33 0 to -0.5% down 0 0 0 0 0 0 1 200.00 66.67 33.33 0 to -0.5% down 0 0 0 0 0 1 0 133.33 66.67 33.33 0 to -0.5% down 0 0 0 0 0 1 1 166.67 66.67 33.33 0 to -0.5% down 0 0 0 0 1 0 0 200.00 66.67 33.33 0 to -0.5% down 0 0 0 0 1 0 1 400.00 66.67 33.33 0 to -0.5% down 0 0 0 0 1 1 0 266.67 66.67 33.33 0 to -0.5% down 0000111 333.33 66.67 33.33 0 to -0.5% down 0 0 0 1 0 0 0 100.99 67.33 33.66 0.25% center 0 0 0 1 0 0 1 201.98 67.33 33.66 0.25% center 0 0 0 1 0 1 0 134.65 67.33 33.66 0.25% center 0001011 168.31 67.32 33.66 0.25% center 0 0 0 1 1 0 0 115.00 76.67 38.33 no spread 0 0 0 1 1 0 1 230.00 76.67 38.33 no spread 0 0 0 1 1 1 0 153.33 76.66 38.33 no spread 0001111 191.67 76.67 38.33 no spread 0 0 1 0 0 0 0 100.00 66.66 33.33 0.25% center 0 0 1 0 0 0 1 200.00 66.66 33.33 0.25% center 0 0 1 0 0 1 0 133.33 66.66 33.33 0.25% center 0 0 1 0 0 1 1 166.67 71.43 35.71 0.25% center 0 0 1 0 1 0 0 200.00 66.66 33.33 0.25% center 0 0 1 0 1 0 1 400.00 66.66 33.33 0.25% center 0 0 1 0 1 1 0 266.67 66.66 33.33 0.25% center 0010111 333.33 66.66 33.33 0.25% center 0 0 1 1 0 0 0 105.00 69.99 35.00 no spread 0 0 1 1 0 0 1 210.00 69.99 35.00 no spread 0 0 1 1 0 1 0 140.00 69.99 35.00 no spread 0011011 175.00 69.99 35.00 no spread 0 0 1 1 1 0 0 110.00 73.33 36.66 no spread 0 0 1 1 1 0 1 220.00 73.33 36.66 no spread 0 0 1 1 1 1 0 146.66 73.33 36.66 no spread 0011111 183.34 73.33 36.66 no spread bit6 bit5
6 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 table1: quadrom frequency selection table (continued) bit4 bit3 bit2 bit1 bit0 cpu agp pci spread fs4fs3fs2fs1fs0 mhz mhz mhz % 0 1 0 0 0 0 0 103.00 68.66 34.33 no spread 0 1 0 0 0 0 1 206.00 68.66 34.33 no spread 0 1 0 0 0 1 0 137.33 68.66 34.33 no spread 0 1 0 0 0 1 1 171.67 68.66 34.33 no spread 0 1 0 0 1 0 0 228.89 68.66 34.33 no spread 0 1 0 0 1 0 1 412.00 68.66 34.33 no spread 0 1 0 0 1 1 0 274.67 68.66 34.33 no spread 0100111 343.33 68.66 34.33 no spread 0 1 0 1 0 0 0 105.00 69.99 35.00 no spread 0 1 0 1 0 0 1 210.00 69.99 35.00 no spread 0 1 0 1 0 1 0 140.00 69.99 35.00 no spread 0 1 0 1 0 1 1 175.00 69.99 35.00 no spread 0 1 0 1 1 0 0 233.33 69.99 35.00 no spread 0 1 0 1 1 0 1 420.00 69.99 35.00 no spread 0 1 0 1 1 1 0 280.00 69.99 35.00 no spread 0101111 350.00 69.99 35.00 no spread 0 1 1 0 0 0 0 107.00 71.33 35.66 no spread 0 1 1 0 0 0 1 214.00 71.33 35.66 no spread 0 1 1 0 0 1 0 142.66 71.33 35.66 no spread 0 1 1 0 0 1 1 178.34 71.33 35.66 no spread 0 1 1 0 1 0 0 237.78 71.33 35.66 no spread 0 1 1 0 1 0 1 428.00 71.33 35.66 no spread 0 1 1 0 1 1 0 285.34 71.33 35.66 no spread 0110111 356.66 71.33 35.66 no spread 0 1 1 1 0 0 0 110.00 73.33 36.66 no spread 0 1 1 1 0 0 1 220.00 73.33 36.66 no spread 0 1 1 1 0 1 0 146.66 73.33 36.66 no spread 0 1 1 1 0 1 1 183.34 73.33 36.66 no spread 0 1 1 1 1 0 0 244.44 73.33 36.66 no spread 0 1 1 1 1 0 1 440.00 73.33 36.66 no spread 0 1 1 1 1 1 0 293.34 73.33 36.66 no spread 0111111 366.66 73.33 36.66 no spread bit6 bit5
7 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 table1: quadrom frequency selection table (continued) bit4 bit3 bit2 bit1 bit0 cpu agp pci spread fs4fs3fs2fs1fs0 mhz mhz mhz % 1 0 0 0 0 0 0 95.00 63.33 31.66 no spread 1 0 0 0 0 0 1 190.00 63.33 31.66 no spread 1 0 0 0 0 1 0 126.66 63.33 31.66 no spread 1 0 0 0 0 1 1 158.34 63.33 31.66 no spread 1 0 0 0 1 0 0 211.11 63.33 31.66 no spread 1 0 0 0 1 0 1 380.00 63.33 31.66 no spread 1 0 0 0 1 1 0 253.34 63.33 31.66 no spread 1000111 316.66 63.33 31.66 no spread 1 0 0 1 0 0 0 90.00 59.99 30.00 no spread 1 0 0 1 0 0 1 180.00 59.99 30.00 no spread 1 0 0 1 0 1 0 120.00 59.99 30.00 no spread 1 0 0 1 0 1 1 150.00 59.99 30.00 no spread 1 0 0 1 1 0 0 200.00 59.99 30.00 no spread 1 0 0 1 1 0 1 360.00 59.99 30.00 no spread 1 0 0 1 1 1 0 240.00 59.99 30.00 no spread 1001111 300.00 59.99 30.00 no spread 1 0 1 0 0 0 0 85.00 56.66 28.33 no spread 1 0 1 0 0 0 1 170.00 56.66 28.33 no spread 1 0 1 0 0 1 0 113.33 56.66 28.33 no spread 1 0 1 0 0 1 1 141.67 56.66 28.33 no spread 1 0 1 0 1 0 0 188.89 56.66 28.33 no spread 1 0 1 0 1 0 1 340.00 56.66 28.33 no spread 1 0 1 0 1 1 0 226.67 56.66 28.33 no spread 1010111 283.33 56.66 28.33 no spread 1 0 1 1 0 0 0 80.00 53.33 26.66 no spread 1 0 1 1 0 0 1 160.00 53.33 26.66 no spread 1 0 1 1 0 1 0 106.66 53.33 26.66 no spread 1 0 1 1 0 1 1 133.34 53.33 26.66 no spread 1 0 1 1 1 0 0 177.78 53.33 26.66 no spread 1 0 1 1 1 0 1 320.00 53.33 26.66 no spread 1 0 1 1 1 1 0 213.34 53.33 26.66 no spread 1011111 266.66 53.33 26.66 no spread bit6 bit5
8 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 table1: quadrom frequency selection table (continued) bit4 bit3 bit2 bit1 bit0 cpu agp pci spread fs4fs3fs2fs1fs0 mhz mhz mhz % 1 1 0 0 0 0 0 115.00 76.66 38.33 no spread 1 1 0 0 0 0 1 230.00 76.66 38.33 no spread 1 1 0 0 0 1 0 153.33 76.66 38.33 no spread 1 1 0 0 0 1 1 191.67 76.66 38.33 no spread 1 1 0 0 1 0 0 255.55 76.66 38.33 no spread 1 1 0 0 1 0 1 460.00 76.66 38.33 no spread 1 1 0 0 1 1 0 306.67 76.66 38.33 no spread 1100111 383.33 76.66 38.33 no spread 1 1 0 1 0 0 0 115.00 79.99 40.00 no spread 1 1 0 1 0 0 1 230.00 79.99 40.00 no spread 1 1 0 1 0 1 0 153.33 79.99 40.00 no spread 1 1 0 1 0 1 1 191.67 79.99 40.00 no spread 1 1 0 1 1 0 0 255.55 79.99 40.00 no spread 1 1 0 1 1 0 1 460.00 79.99 40.00 no spread 1 1 0 1 1 1 0 306.67 79.99 40.00 no spread 1101111 383.33 79.99 40.00 no spread 1 1 1 0 0 0 0 78.00 51.99 26.00 no spread 1 1 1 0 0 0 1 156.00 51.99 26.00 no spread 1 1 1 0 0 1 0 104.00 51.99 26.00 no spread 1 1 1 0 0 1 1 130.00 51.99 26.00 no spread 1 1 1 0 1 0 0 173.33 51.99 26.00 no spread 1 1 1 0 1 0 1 312.00 51.99 26.00 no spread 1 1 1 0 1 1 0 208.00 51.99 26.00 no spread 1110111 260.00 51.99 26.00 no spread 1 1 1 1 0 0 0 75.00 50.00 25.00 no spread 1 1 1 1 0 0 1 150.00 50.00 25.00 no spread 1 1 1 1 0 1 0 100.00 50.00 25.00 no spread 1 1 1 1 0 1 1 125.00 50.00 25.00 no spread 1 1 1 1 1 0 0 166.67 50.00 25.00 no spread 1 1 1 1 1 0 1 300.00 50.00 25.00 no spread 1 1 1 1 1 1 0 200.00 50.00 25.00 no spread 1111111 250.00 50.00 25.00 no spread bit6 bit5
9 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 i 2 c table: frequency select register control function bit 7 fs source frequency h/w iic select rw 0 bit 6 fs6 freq select bit 6 rw 0 bit 5 fs5 freq select bit 5 rw 0 bit 4 fs4 freq select bit 4 rw 0 bit 3 fs3 freq select bit 3 rw 0 bit 2 fs2 freq select bit 2 rw 0 bit 1 fs1 freq select bit 1 rw 0 bit 0 fs0 freq select bit 0 rw 0 i 2 c table: spreading and device behavior control register control function bit 7 ss1 spread select 1** rw 0 bit 6 ss0 spread select 0** rw 1 bit 5 ss_en spread enable control rw 1 bit 4 wds_en wd soft reset enable rw 0 bit 3 reserved reserved rw 1 bit 2 cpuclkt/c_itp, cpu1t/c, cpu0t/c output control rw 1 bit 1 cpuclkt/c_1 output control rw 1 bit 0 cpuclkt/c_0 output control rw 1 i 2 c table: output control register control function bit 7 25mhz_0 output control rw 1 bit 6 25mhz_1 output control rw 1 bit 5 cput stop mode 0: cput driven during pd#; 1: tri-stated rw 0 bit 4 reserved reserved rw 1 bit 3 3v66_1 output control rw 1 bit 2 reserved reserved rw 1 bit 1 cpuclkt/c_1 output stop control rw 1 bit 0 cpuclkt/c_0 output stop control rw 1 i 2 c table: output control register control function bit 7 asel1 3v66/pci freq select rw 0 bit 6 pciclk6 output control rw 1 bit 5 pciclk5 output control rw 1 bit 4 pciclk4 output control rw 1 bit 3 pciclk3 output control rw 1 bit 2 pciclk2 output control rw 1 bit 1 pciclk1 output control rw 1 bit 0 pciclk0 output control rw 1 disable enable see table 5: async agp/pci freq table disable enable disable enable disable enable disable enable disable enable free run stoppable disable enable -- free run stoppable disable enable disable enable -- disable enable driven hi-z disable enable disable disable enable enable on off -- 01 = 0.25% reserved pwd - byte 3 pin # name type 0 1 36 35 26 - 42,41 39, 38 20 type pwd 39, 38 byte 2 pin # name 0 1 ** spread program m ing only applies for rom table entries 0001000 to 0001011 and 0010000 to 0010111 - - 45, 44 42,41 on off - pwd - - byte 1 pin # name type 00 = 0.20% 10 = 0.35% - - see table 1: quadrom frequency selection table 01 pwd - byte 0 pin # name type latch inputs iic 01 - - - - - 19 16 15 14 13 12 - -
10 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 table 5: asynchronous 3v66/pci frequency table byte6 bit7 byte3 bit7 3v66/pci frequency 0 0 66.66/33.33 0 1 80.00/40.00 1 0 72.73/36.36 i 2 c table: output control register control function bit 7 48mhz_0 2x output drive 0=2x drive rw 1 bit 6 pci adiv pci async divider cntr rw 0 bit 5 reserved reserved rw 1 bit 4 3v66_0 output control rw 1 bit 3 reserved reserved rw 1 bit 2 pciclk_f2 output control rw 1 bit 1 pciclk_f1 output control rw 1 bit 0 pciclk_f0 output control rw 1 i 2 c table: reserved register control function bit 7 reserved reserved rw 0 bit 6 mode sel1 rw 0 bit 5 mode sel0 rw 0 bit 4 3v66_2 output control rw 1 bit 3 m pll2 div3 rw x bit 2 m pll2 div2 rw x bit 1 m pll2 div1 rw x bit 0 m pll2 div0 rw x -- see table 4: mode selection table disable enable disable enable disable enable -- disable enable agp/2 pll3 freq/24 disable enable -- the decimal representation of m pll2 div (3:0) + 2 is equal to ref divider value for pll2 01 01 - - - - pwd 7 byte 5 pin # name type pwd - 2x drive normal name type byte 4 pin # pll mode selection bits m divider programming bits for async mode 2&3 - 25 - - - 29 - 9 8 - table 4: mode selection table mode standard overclock mode(i) cpu overclock mode(ii) graphic overclock mode(iii) iic control byte 5 bit(6:5) = 00 byte 5 bit(6:5) = 01 byte 5 bit(6:5) = 10 25mhz from? pll3 pll3 pll1 3v66/pci from? pll1 (needed to be align w/ cpu) pll3 pll3 spreading cpu/3v66/pci have spread only cpu clocks have spread. only cpu clocks have spread. i 2 c table: vendor & revision id register control function bit 7 asel0 3v66/pci freq select rw 0 bit 6 n pll2 div6 rw x bit 5 n pll2 div5 rw x bit 4 n pll2 div4 rw x bit 3 n pll2 div3 rw x bit 2 n pll2 div2 rw x bit 1 n pll2 div1 rw x bit 0 n pll2 div0 rw x the decimal representation of n pll2 div (6:0) + 8 is equal to vco divider value for pll2. byte 6 pin # name - - - pwd - - n divider programming bits for async mode 2&3 - - - see table 5: async agp/pci freq table 01 type
11 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 i 2 c table: vendor & revision id register control function bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 i 2 c table: byte count register control function bit 7 bc7 rw 0 bit 6 bc6 rw 0 bit 5 bc5 rw 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 1 bit 1 bc1 rw 1 bit 0 bc0 rw 1 i 2 c table: watchdog timer register control function bit 7 wd7 wd timer bit 7 rw 0 bit 6 wd6 wd timer bit 6 rw 0 bit 5 wd5 wd timer bit 5 rw 0 bit 4 wd4 wd timer bit 4 rw 0 bit 3 wd3 wd timer bit 3 rw 1 bit 2 wd2 wd timer bit 2 rw 0 bit 1 wd1 wd timer bit 1 rw 1 bit 0 wd0 wd timer bit 0 rw 1 i 2 c table: vco control select bit & wd timer control register control function bit 7 m/nen m/n programming enable rw 0 bit 6 wden watchdog enable r 0 bit 5 wdfsen wd safe frequency mode rw 0 bit 4 wd sf4 rw 0 bit 3 wd sf3 rw 0 bit 2 wd sf2 rw 0 bit 1 wd sf1 rw 0 bit 0 wd sf0 rw 0 -- 1 writing to this register will configure how many bytes will be read back, default is 0f = 15 bytes. 0 -- -- -- -- 1 -- -- -- pwd 01 disable enable 01 byte 9 pin # name type disable enable latched fs/byte0 these bits represent x*290ms the watchdog timer waits before it goes to alarm mode. default is 11 x 293ms = 3.2s. writing to these bit will configure the safe frequency as byte0 bit (4:0). wd b10 b(4:0) - watch dog safe freq programming bits - - - - - - pwd - byte 10 pin # name type - - - - - pwd - byte count programming b(7:0) - - - - - - - type - type - vendor id - - name byte 8 pin # pwd - revision id - - - byte 7 pin # name 0 - - -
12 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 i 2 c table: vco frequency control register control function bit 7 n div8 n divider prog bit 8 rw x bit 6 m div6 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x i 2 c table: vco frequency control register control function bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 rw x bit 1 n div1 rw x bit 0 n div0 rw x i 2 c table: spread spectrum control register control function bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x i 2 c table: spread spectrum control register control function bit 7 reserved reserved r 0 bit 6 reserved reserved r 0 bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x 01 - 01pwd 0 these spread spectrum bits in byte 13 and 14 will program the spr ead pecentage. it is recommended to use ics spread % table for spread programming. these spread spectrum bits in byte 13 and 14 will program the spr ead pecentage. it is recommended to use ics spread % table for spread programming. 01 -- - the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(8:0)+8] / [mdiv(6:0)+2] 1 the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(8:0)+8] / [mdiv(6:0)+2] - - spread spectrum programming b(13:8) - - - - - pwd - byte 14 pin # name type pwd - spread spectrum programming b(7:0) - - - - - - - name type - - byte 13 pin # pwd - n divider programming b(8:0) - - - - - byte 12 pin # name type - m divider programming bits - - - - - - - byte 11 pin # name type
13 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 i 2 c table: output divider control register control function bit 7 25mhz div3 rw 0000:/2 0100:/4 1000:/8 1100:/16 x bit 6 25mhz div2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 5 25mhz div1 rw 0010:/5 0110:/10 1010:/20 1110:/40 x bit 4 25mhz div0 rw 0011:/7 0111:/14 1011:/28 1111:/56 x bit 3 cpu div3 rw 0000:/2 0100:/4 1000:/8 1100:/16 x bit 2 cpu div2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 1 cpu div1 rw 0010:/5 0110:/10 1010:/20 1110:/40 x bit 0 cpu div0 rw 0011:/7 0111:/14 1011:/28 1111:/56 x i 2 c table: output divider control register control function bit 7 reserved rw x bit 6 reserved rw x bit 5 reserved rw x bit 4 reserved rw x bit 3 3v66div3 rw 0000:/2 0100:/4 1000:/8 1100:/16 x bit 2 3v66div2 rw 0001:/3 0101:/6 1001:/12 1101:/24 x bit 1 3v66div1 rw 0010:/5 0110:/10 1010:/20 1110:/40 x bit 0 3v66div0 rw 0011:/7 0111:/14 1011:/28 1111:/56 x i 2 c table: output divider control register control function bit 7 reserved reserved rw x bit 6 reserved reserved rw x bit 5 reserved reserved rw x bit 4 cpuinv cpu phase invert rw 1 bit 3 reserved reserved rw 1 bit 2 reserved reserved rw 1 bit 1 reserved reserved rw 1 bit 0 reserved reserved rw 1 i 2 c table: group skew control register control function bit 7 reserved reserved rw 0 bit 6 reserved reserved rw 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 reserved reserved rw 0 bit 2 reserved reserved rw 0 bit 1 reserved reserved rw 0 bit 0 reserved reserved rw 0 -- -- -- -- -- -- -- - default - inverse -- -- -- 1 -- -- -- 01 pin # - - - - - - - - - - - - - - - pwd - name type 0 1 -- byte 18 pwd - byte 17 pin # name type 0 3v66/pci divider ratio programming bits for mode 1 - - - pwd - name type 0 1 byte 16 pin # - - - - cpudivider ratio programming bits - - - reserved - pwd - 25mhz divider ratio programming bits - - - byte 15 pin # name type - - - - - - -
14 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 i 2 c table: group skew control register control function bit 7 3v66skw3 rw 0000:0 0100:150 1000:300 1100:450 0 bit 6 3v66skw2 rw 0001:n/a 0101:n/a 1001:n/a 1101:600 0 bit 5 3v66skw1 rw 0010:n/a 0110:n/a 1010:n/a 1110:750 0 bit 4 3v66skw0 rw 0011:n/a 0111:n/a 1011:n/a 1111:900 0 bit 3 pciskw3 rw 0000:0 0100:150 1000:300 1100:450 1 bit 2 pciskw2 rw 0001:n/a 0101:n/a 1001:n/a 1101:600 1 bit 1 pciskw1 rw 0010:n/a 0110:n/a 1010:n/a 1110:750 0 bit 0 pciskw0 rw 0011:n/a 0111:n/a 1011:n/a 1111:900 0 i 2 c table: group skew control register control function bit 7 pciskw3 rw 0000:0 0100:150 1000:300 1100:450 1 bit 6 pciskw2 rw 0001:n/a 0101:n/a 1001:n/a 1101:600 1 bit 5 pciskw1 rw 0010:n/a 0110:n/a 1010:n/a 1110:750 0 bit 4 pciskw0 rw 0011:n/a 0111:n/a 1011:n/a 1111:900 0 bit 3 reserved reserved rw 0 bit 2 reserved reserved rw 0 bit 1 reserved reserved rw 0 bit 0 reserved reserved rw 0 i 2 c table: slew rate control register control function bit 7 pcifstr1 1 bit 6 pcifstr0 1 bit 5 pcifstr1 1 bit 4 pcifstr0 1 bit 3 reserved reserved rw 1 bit 2 reserved reserved rw 1 bit 1 agpstr1 rw 1 bit 0 agpstr0 rw 1 i 2 c table: slew rate control register control function bit 7 rw 1 bit 6 rw 0 bit 5 pcifstr1 1 bit 4 pcifstr0 1 bit 3 pcifstr1 1 bit 2 pcifstr0 1 bit 1 pcifstr1 1 bit 0 pcifstr0 1 pciclk (6) strength control rw - 01 = 0.75x 11 = 1.00x 00 = 0.63x -- pwd 01 01 -- -- - 01 byte 20 pin # name type 0 1 cpu-pci 7 step skew control (ps) - 01 = 0.75x 10 = 0.88x -- 00 = 0.70x 10 = 0.90x 11 = 1.00x -- - pin # - - - - - - - - - - - - - - - - - pwd agpclk strength control - byte 22 pin # name - pwd - pciclkf (2:0) strength control - byte 21 pin # name type rw 00 = 0.63x cpu-pci f(2:0) 7 step skew control (ps) - - - - - pwd - cpu-3v66 7 step skew control (ps) - - - byte 19 name type 00 = 0.63x pciclk (1:0) strength control 00 = 0.63x 10 = 0.88x 01 = 0.75x 11 = 1.00x 01 = 0.80x 11 = 1.00x 01 = 0.75x 11 = 1.00x type rw 00 = 0.63x 10 = 0.88x ref_slw ref slew rate control pciclk (5) strength control 00 = medium 10 = strong 01 = weak 11 = n/a 10 = 0.88x pciclk (4:2) strength control 10 = 0.88x 01 = 0.75x 11 = 1.00x rw rw
15 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 i 2 c table: output control register control function bit 7 48mhz_0 output control rw 1 bit 6 24_48mhz output control rw 1 bit 5 ref1 output control rw 1 bit 4 ref0 output control rw 1 bit 3 ref2 output control rw 1 bit 2 48mhz_1 output control rw 1 bit 1 reserved reserved rw 0 bit 0 reserved reserved rw 0 i 2 c table: read back register control function bit 7 wdhrb wd hard alarm status read back rx bit 6 wdsrb wd soft alarm status read back rx bit 5 reserved reserved r 0 bit 4 fs4rb fs4 read back r x bit 3 fs3rb fs3 read back r x bit 2 fs2rb fs2 read back r x bit 1 fs1rb fs1 read back r x bit 0 fs0rb fs0 read back r x -- -- -- -- -- -- -- -- -- enable disable enable -- disable enable disable enable 01 type pwd 01 disable enable disable enable disable pwd type byte 24 - - - - pin # - byte 23 pin # - name name - - - - - - - - - -
16 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. core operating voltage . . . . . . . . . . . . . . . . . . . 4.6 v i/o operating voltage . . . . . . . . . . . . . . . . . . . . . 3.6v lo gic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd + 0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3v +/-5% 2 v dd + 0.3 v input mid voltage v mi d 3.3v +/-5% 1 1.8 v input low voltage v il 3.3v +/-5% v ss -0.3 0.8 v input high current i ih v in = v d d -5 5 ua i il1 v in = 0 v; inputs with no pull- up resistors -5 ua i il2 v in = 0 v; inputs with pull-up resistors -200 ua operating supply current i dd3.3op full active, c l = full load; 350 ma all diff pairs driven 35 ma all differential pairs tri-stated 12 ma input frequency 3 f i v dd = 3.3 v 14.31818 mhz 3 pin inductance 1 l p in 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization 1,2 t stab from vdd power-up or de- assertion of pd# to 1st clock. 1.8 ms 1,2 modulation frequency triangular modulation 30 33 khz 1 1 guaranteed by design, not 100% tested in production. 2 see timing diagrams for timing requirements. i dd3.3pd 3 input frequency should be measured at the ref output pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs. input capacitance 1 input low current powerdown current
17 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 electrical characteristics - cpu & src 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3v +/-5%; c l =2pf parameter symbol conditions min typ max units notes current source output im p edance zo 1 v o = v x 3000 ? 1 voltage high vhigh 660 850 1 voltage low vlow -150 150 1 max volta g e vovs 1150 1 min volta g evuds -300 1 crossin g volta g e ( abs ) vcross ( abs ) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 140 mv 1 lon g accurac y pp msee t p eriod min-max values -300 300 pp m1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 v t = 50% 100 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 125 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended signal using absolute value. mv
18 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 electrical characteristics - pciclk t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y ppm see tperiod min-max values -300 300 ppm 1,2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh@min = 1.0 v -33 ma v oh@max = 3.135 v -33 ma v ol@min = 1.95 v 30 ma v ol@max = 0.4 v 38 ma edge rate rising edge rate 1 4 v/ns 1 ed g e rate fallin g ed g e rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 500 ps 1 jitter t jcyc-cyc v t = 1.5 v 3v66 250 ps 1 1 guaranteed b y desi g n, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz output high current i oh output low current i ol electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh@min = 1.0 v -33 ma v oh@max = 3.135 v -33 ma v ol @min = 1.95 v 30 ma v ol@max = 0.4 v 38 ma edge rate rising edge rate 1 4 v/ns 1 edge rate falling edge rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 250 ps 1 jitter t jcyc-cyc v t = 1.5 v 3v66 250 ps 1 1 guaranteed by design, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz output high current i oh output low current i ol
19 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 electrical characteristics - ref-14.318mhz t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1 output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 2 ns 1 fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 2 ns 1 skew t sk1 1 v t = 1.5 v 500 ps 1 duty cycle d t1 1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc 1 v t = 1.5 v 1000 ps 1 1 guaranteed by design, not 100% tested in production. electrical characteristics - 48mhz, 24mhz t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y ppm see tperiod min-max values -200 200 ppm 1,2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh@min = 1.0 v -33 ma v oh@max = 3.135 v -33 ma v ol @min = 1.95 v 30 ma v ol@max = 0.4 v 38 ma ed g e rate risin g ed g e rate 1 2 v/ns 1 edge rate falling edge rate 1 2 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 long term jitter 125us period jitter (8khz frequency modulation amplitude) 6ns1 1 guaranteed by design, not 100% tested in production. output low current i ol 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref out p ut is at 14.31818mhz output high current i oh
20 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
21 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 ordering information ICS952906Aflft index area index area 1 2 n d h x 45 e1 e seating plane seating plane a1 a e - c - b .10 (.004) c .10 (.004) c c l min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) example: designation for tape and reel packaging lead free, rohs compliant (optional) package type f = ssop revision designator device type prefix ics = standard device ics xxxx a f lf- t
22 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 ordering information ICS952906Aglft example: designation for tape and reel packaging lead free, rohs compliant (optional) package type g = tssop revision designator device type prefix ics = standard device ics xxxx a g lf- t min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 n d mm. d ( inch ) ref erence do c.: jedec pub licat io n 9 5, m o- 153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions index area index area 12 1 n d e1 e sea ting plane sea ting plane a1 a1 a a2 a2 e -c- -c- b c l aaa c
23 integrated circuit systems, inc. ICS952906A 1236a?08/06/07 revision history rev. issue date description page # n/a 06/15/06 initial release - 0.1 08/29/06 updated i2c 13 a 08/06/07 1. updated 48/24mhz electrical characteristics 2. final release 19

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